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DATA SHEET
MOS INTEGRATED CIRCUIT
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
4-BIT SINGLE-CHIP MICROCONTROLLERS
The PD750068 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing capability comparable to that of an 8-bit microcontroller. The PD750068 provides more CPU functions compared to the 75X Series and realizes high-speed operation at the low voltage of 1.8 V, making it ideal for battery-driven applications. This device has on-chip A/D converters, and sophisticated timers capable of operating as a 16-bit timer. The PD750068(A) has a higher reliability than the PD750068. A version with on-chip one-time PROM, PD75P0076, is also available for the evaluation during system development or for small-scale production. Detailed function descriptions are provided in the following user's manual. Be sure to read the document before designing.
PD750068 User's Manual: U10670E
Features
O O
Low-voltage operation: VDD = 1.8 to 5.5 V On-chip memory * Program memory (ROM): 4096 x 8 bits (PD750064, 750064(A)) 6144 x 8 bits (PD750066, 750066(A)) 8192 x 8 bits (PD750068, 750068(A)) * Data memory (RAM): 512 x 4 bits
O
O
O O
Variable instruction execution time for high-speed operation and power-saved operation * 0.95, 1.91, 3.81, 15.3 s (@ 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0-MHz operation) * 122 s (@ 32.768-kHz operation) Internal low-voltage A/D converters (AVREF = 1.8 to 5.5 V) 8-bit resolution x 8 channels Small packages (shrink SOP, shrink DIP) Uses instructions of 75X Series for easy replacement
Applications
O
O
PD750064, 750066, 750068 Cordless phones, audio-visual equipment, home appliances, office machines, fitness machines, meters, gas ranges, etc. PD750064(A), 750066(A), 750068(A) Electrical equipment for automobiles
The PD750064, 750066, 750068 and PD750064(A), 750066(A), 750068(A) differ only in quality grade. In this manual, the PD750068 is described as typical product unless otherwise specified. Users of other than the PD750068 should read the PD750068 as referring to the pertinent product. When the description differs among the PD750064, 750066, and 750068, they also refer to the pertinent (A) products.
PD750064 PD750064(A), PD750066 PD750066(A), PD750068 PD750068(A)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U10165EJ2V0DS00 (2nd edition) Date Published April 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1995
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Ordering Information
Part Number Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Quality Grade Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special
PD750064CU-xxx PD750064GT-xxx PD750066CU-xxx PD750066GT-xxx PD750068CU-xxx PD750068GT-xxx PD750064CU(A)-xxx PD750064GT(A)-xxx PD750066CU(A)-xxx PD750066GT(A)-xxx PD750068CU(A)-xxx PD750068GT(A)-xxx
Remark
xxx indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Differences between PD75006x and PD75006x(A)
Part Number Item Quality grade
PD750064 PD750066 PD750068
Standard
PD750064(A) PD750066(A) PD750068(A)
Special
2
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Functional Outline
Item Instruction execution time Function * 0.95 s, 1.91 s, 3.81 s, 15.3 s (@ 4.19-MHz operation with main system clock) * 0.67 s, 1.33 s, 2.67 s, 10.7 s (@ 6.0-MHz operation with main system clock) * 122 s (@ 32.768-kHz operation with subsystem clock) ROM 4096 x 8 bits (PD750064) 6144 x 8 bits (PD750066) 8192 x 8 bits (PD750068) RAM General-purpose register 512 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 12 On-chip pull-up resistors can be specified by software: 7 Also used for analog input pins: 4 On-chip pull-up resistors can be specified by software: 12 Also used for analog input pins: 4 13 V withstand voltage On-chip pull-up resistors can be specified by mask option 32 4 * * * channels 8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter) Basic interval timer/watchdog timer: 1 channel Watch timer: 1 channel
On-chip memory
Input/ output port
CMOS input
CMOS input/output
12
N-ch open-drain input/output pins Total Timer
8
Serial interface
* 3-wire serial I/O mode *** MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode 8-bit resolution x 8 channels (1.8 V AVREF VDD) 16 bits * , 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19-MHz operation with main system clock) * , 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0-MHz operation with main system clock) * 2 kHz, 4 kHz, 32 kHz (@ 4.19-MHz operation with main system clock or @ 32.768-kHz operation with subsystem clock) * 2.93 kHz, 5.86 kHz, 46.9 kHz (@ 6.0-MHz operation with main system clock) External: 3, Internal: 4 External: 1, Internal: 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode TA = -40 to +85C VDD = 1.8 to 5.5 V * 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) * 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
A/D converter Bit sequential buffer Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupt Test input System clock oscillator
Standby function Operating ambient temperature Power supply voltage Package
Data Sheet U10165EJ2V0DS00
3
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
CONTENTS
1. PIN CONFIGURATION (Top View) ...................................................................................................... 6 2. BLOCK DIAGRAM ................................................................................................................................ 7 3. PIN FUNCTION ..................................................................................................................................... 8 3.1 Port Pins ...................................................................................................................................... 8 3.2 Non-port Pins ............................................................................................................................ 10 3.3 Pin Input/Output Circuits ......................................................................................................... 12 3.4 Recommended Connection of Unused Pins .......................................................................... 15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 16 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 16 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 17 5. MEMORY CONFIGURATION ............................................................................................................. 18 6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 23 6.1 Port ............................................................................................................................................. 23 6.2 Clock Generator ........................................................................................................................23 6.3 Subsystem Clock Oscillator Control Function ...................................................................... 25 6.4 Clock Output Circuit .................................................................................................................26 6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 27 6.6 Watch Timer ..............................................................................................................................28 6.7 Timer/Event Counter .................................................................................................................29 6.8 Serial Interface .......................................................................................................................... 32 6.9 A/D Converter ............................................................................................................................ 33 6.10 Bit Sequential Buffer ................................................................................................................ 34 7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 35 8. STANDBY FUNCTION ........................................................................................................................37 9. RESET FUNCTION .............................................................................................................................38 10. MASK OPTION ...................................................................................................................................41 11. INSTRUCTION SET ............................................................................................................................ 42 12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 55 13. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................. 68 14. PACKAGE DRAWINGS ...................................................................................................................... 70 15. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 72
4
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
APPENDIX A. PD75068, 750068 AND 75P0076 FUNCTIONAL LIST .................................................. 73 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 75 APPENDIX C. RELATED DOCUMENTS ................................................................................................. 79
Data Sheet U10165EJ2V0DS00
5
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
1. PIN CONFIGURATION (Top View)
* 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
PD750064CU-xxx, PD750064CU(A)-xxx PD750066CU-xxx, PD750066CU(A)-xxx PD750068CU-xxx, PD750068CU(A)-xxx
* 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
PD750064GT-xxx, PD750064GT(A)-xxx PD750066GT-xxx, PD750066GT(A)-xxx PD750068GT-xxx, PD750068GT(A)-xxx
XT1 XT2 RESET X1 X2 P33 P32 P31 P30 AVSS P63/KR3/AN7 P62/KR2/AN6 P61/KR1/AN5 P60/KR0/AN4 P113/AN3 P112/AN2 P111/AN1 P110/AN0 AVREF IC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS P40 P41 P42 P43 P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/TI1/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ
IC: Internally Connected (Connect pin directly to VDD).
Pin Identification
AN0 to AN7 AVREF AVSS BUZ IC INT2 KR0 to KR3 P00 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 : Analog Input 0 to 7 : Analog Reference : Analog Ground : Buzzer Clock : Internally Connected : External Test Input 2 : Key Return 0 to 3 : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 P60 to P63 P110 to P113 PCL PTO0, PTO1 RESET SB0, SB1 SCK SI SO TI0, TI1 VDD VSS X1, X2 XT1, XT2 : Port 6 : Port 11 : Programmable Clock : Programmable Timer Output 0, 1 : Reset Input : Serial Data Bus 0, 1 : Serial Clock : Serial Input : Serial Output : Timer Input 0, 1 : Positive Power Supply : Ground : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
6
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
2. BLOCK DIAGRAM
Basic interval timer/watchdog timer INTBT BUZ/P23 Watch timer INTW 8-bit timer/ event counter#0 8-bit timer/ event counter#1 INTW INTT0
Program counter Cascaded 16-bit timer/ event counter
Port 0
4
P00 to P03
SP (8) ALU CY
Port 1
4
P10 to P13
Port 2
4
P20 to P23
Port 3 SBS BANK Port 4
4
P30 to P33
TI0/P13 PTO0/P20
4
P40 to P43
TI1/P12/INT2 PTO1/P21
General reg.
Port 5
4
P50 to P53
INTT1 SI/SB1/P03 SO/SB0/P02 SCK/P01 INTCSI TOUT0 INT0/P10 INT1/P11 INT4/P00 INT2/P12/TI1 KR0/P60 to 4 KR3/P63 AN0/P110 to 4 AN3/P113 AN4/P60 to 4 AN7/P63 AVREF AVSS A/D converter Interrupt control Clocked serial interface
Program memoryNote (ROM)
Port 6 Data memory (RAM) 512 x 4 bits
4
P60 to P63
Port 11
4
P110 to P113
Decode and control
Bit seq. buffer (16)
fx/2N
Clock output control
CPU Clock System clock generator Sub Main Stand by control
Clock divider
PCL/P22
XT1 XT2 X1 X2
IC
VDD
VSS RESET
Note The ROM capacity varies depending on the product.
Data Sheet U10165EJ2V0DS00
7
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
3. PIN FUNCTION 3.1 Port Pins (1/2)
Alternate Function INT4 SCK SO/SB0 SI/SB1 INT0 INT1 TI1/INT2 TI0 Input/Output PTO0 PTO1 PCL BUZ Input/Output - Programmable 4-bit input/output port (PORT3). This port can be specified for input/output in 1-bit units. Connection of on-chip pull-up resistor can be specified by software in 4-bit units. N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be contained in 1-bit units (mask option). Withstand voltage is 13 V in open-drain mode. N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained in 1-bit units (mask option). Withstand voltage is 13 V in open-drain mode. No Input E-B 4-bit input/output port (PORT2). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. No Input E-B 4-bit input port (PORT1). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. P10/INT0 can select noise elimination circuit. No Input 8-bit I/O No I/O Circuit TypeNote 1 -A -B -C -C
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 to P33
Input/Output Input Input/Output Input/Output Input/Output Input
Function 4-bit input port (PORT0). For P01 to P03, connection of on-chip pullup resistors can be specified by software in 3-bit units.
After Reset Input
P40 to P43Note 2 Input/Output
-
Yes
High level (when pull-up resistors are provided) or highimpedance High level (when pull-up resistors are provided) or highimpedance
M-D
P50 to P53Note 2 Input/Output
-
M-D
Notes 1. 2.
Circuit types enclosed in brackets indicate the Schmitt trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low-level input leakage current increases when input or bit manipulation instruction is executed.
8
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
3.1 Port Pins (2/2)
Alternate Function KR0/AN4 KR1/AN5 KR2/AN6 KR3/AN7 Input AN0 AN1 AN2 AN3 4-bit input port (PORT11). No Input Y-A 8-bit I/O No I/O Circuit Type Note -D
Pin Name P60 P61 P62 P63 P110 P111 P112 P113
Input/Output Input/Output
Function Programmable 4-bit input/output port (PORT6). This port can be specified for input/output in 1-bit units. Connection of on-chip pull-up resistors can be specified by software in 4-bit units.
After Reset Input
Note
Circuit types enclosed in brackets indicate the Schmitt trigger input.
Data Sheet U10165EJ2V0DS00
9
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
3.2 Non-port Pins (1/2)
Alternate Function P13 P12/INT2 Output P20 P21 P22 P23 Clock output Optional frequency output (for buzzer output or system clock trimming) Serial clock input/output Serial data output Serial data bus input/output P03 Serial data input Serial data bus input/output P00 Edge detection vectored interrupt input (both rising edge and falling edge detection) Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 can select noise elimination circuit. Rising edge detection testable input Noise elimination circuit/asynchronous selection Asynchronous Asynchronous Input -C Input -C Input -A -B I/O Circuit Type Note -C
Pin Name TI0 TI1 PTO0 PTO1 PCL BUZ
Input/Output Input
Function Inputs external event pulses to the timer/event counter. Timer/event counter output
After Reset Input
Input
E-B
SCK SO SB0 SI SB1 INT4
Input/Output Output Input/Output Input Input/Output Input
P01 P02
INT0
Input
P10
-C
INT1 INT2 Input
P11 P12/TI1
KR0 to KR3
Input
P60/AN4 to P63/AN7
Falling edge detection testable input
Input
-D
AN0 to AN3 AN4 to AN7
Input
P110 to P113 P60/KR0 to P63/KR3
Analog signal input
Input
Y-A -D
AVREF AVSS
- -
- -
A/D converter reference voltage A/D converter reference GND potential
- -
Z-N Z-N
Note
Circuit types enclosed in brackets indicate the Schmitt trigger input.
10
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
3.2 Non-port Pins (2/2)
Alternate Function - I/O Circuit Type Note -
Pin Name X1 X2
Input/Output Input -
Function Crystal/ceramic connection pin for the main system clock oscillation. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. Crystal connection pin for the subsystem clock oscillation. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. System reset input (low-level active) Internally connected. Connect directly to VDD. Positive power supply Ground potential
After Reset -
XT1 XT2
Input -
-
-
-
RESET IC VDD VSS
Input - - -
- - - -
- - - -
- - -
Note
Circuit types enclosed in brackets indicate the Schmitt trigger input.
Data Sheet U10165EJ2V0DS00
11
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
3.3 Pin Input/Output Circuits
The PD750068 pin input/output circuits are shown schematically. (1/3)
TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT
CMOS standard input buffer
Push-pull output that can be placed in output high-impedance (both P-ch and N-ch off).
TYPE B
TYPE E-B VDD P.U.R. P.U.R. enable IN data Type D output disable P-ch
IN/OUT
Type A
Schmitt-triggered input with hysteresis characteristics P.U.R. : Pull-Up Resistor
TYPE B-C VDD P.U.R. P.U.R. enable
TYPE F-A VDD P.U.R. P.U.R. enable data output disable IN
Type B
P-ch
P-ch
IN/OUT Type D
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
12
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
(2/3)
TYPE F-B VDD P.U.R. P.U.R. enable output disable (P) data output disable output disable (N) VDD P-ch IN/OUT AVSS N-ch input enable P-ch IN VDD Sampling C AVSS Reference voltage (from the voltage tap of the series resistor string) P-ch N-ch + - VDD TYPE Y
P.U.R. : Pull-Up Resistor
TYPE M-C VDD P.U.R.
TYPE Y-A
IN instruction P.U.R. enable P-ch IN/OUT Type A data output disable Input butfer N-ch IN Type Y
P.U.R. : Pull-Up Resistor TYPE M-D P.U.R. (Mask Option) IN/OUT data output disable Input instruction VDD P-ch P.U.R.Note Voltage limitation (+13 V circuit withstand voltage) Note This pull-up resistor operates only when an input instruction is executed without a pull-up resistor connected using the mask option (current flows from VDD to the pin when the pin is low). N-ch (+13 V withstand voltage)
VDD
Data Sheet U10165EJ2V0DS00
13
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
(3/3)
TYPE Y-D VDD AVREF P.U.R. P.U.R. enable P-ch TYPE Z-N
data output disable Type D
IN/OUT Reference voltage
Type B
ADEN Type Y P.U.R.: Pull-Up Resistor
N-ch
AVSS
14
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Recommended Connection of Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/INT2 P13/TI0 P20/PTO0 P21/PTO1 Output state: P22/PCL P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60/KR0/AN4 to P63/KR3/AN7 Connect to VSS (do not connect a pull-up resistor of mask option). Input state: Output state: P110/AN0 to P113/AN3 XT1 XT2 IC AVREF AVSS
Note
Recommended Connection Connect to VSS or VDD. Independently connect to VSS or VDD via a resistor.
Connect to VSS. Connect to VSS or VDD.
Input state:
Independently connect to VSS or VDD via a resistor. Leave open.
Independently connect to VSS or VDD via a resistor. Leave open.
Connect directly to VSS or VDD. Connect to VSS. Leave open. Connect directly to VDD. Connect to VSS.
Note
Note
When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor).
Data Sheet U10165EJ2V0DS00
15
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode
The CPU of the PD750068 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). * Mk I mode: * Mk II mode: Upward compatible with PD75068. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. Incompatible with PD75068. Can be used in all the 75XL CPUs including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I Mode Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 2 bytes 3 bytes Mk II Mode
Not available
Available
3 machine cycles 2 machine cycles
4 machine cycles 3 machine cycles
Caution
The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 Kbytes. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility.
16
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 100xBNote at the beginning of a program. When using the Mk II mode, it must be initialized to 000xBNote. Note Set the desired value in the x position. Figure 4-1. Stack Bank Select Register Format
Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS
SBS2 SBS1
Stack area specification 0 0 0 1 Memory bank 0 Memory bank 1
Other than above setting prohibited
0
0 must be set in the bit 2 position.
Mode switching specification 0 1 Mk II mode Mk I mode
Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode.
Data Sheet U10165EJ2V0DS00
17
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
5. MEMORY CONFIGURATION
Program memory (ROM) .... 4096 x 8 bits (PD750064) .... 6144 x 8 bits (PD750066) .... 8192 x 8 bits (PD750068) * Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. * Addresses 0002H to 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt processing can start from any address. * Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. Data memory (RAM) * Data area .... 512 words x 4 bits (000H to 1FFH)
* Peripheral hardware area .... 128 words x 4 bits (F80H to FFFH)
18
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 5-1. Program Memory Map (PD750064)
Address 7 6 5 0 4 0 Internal reset start address Internal reset start address 0 0 2 H MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 0 4 H MBE RBE 0 0 INT0 INT0 0 0 6 H MBE RBE 0 0 INT1 INT1 0 0 8 H MBE RBE 0 0 INTCSI INTCSI 0 0 A H MBE RBE 0 0 INTT0 INTT0 0 0 C H MBE RBE 0 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) CALLF ! faddr instruction entry address
0 0 0 H MBE RBE
Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16
020H GETI instruction reference table 07FH 080H
BRCB !caddr instruction branch address
7FFH 800H
Branch destination address and subroutine entry address when GETI instruction is executed
FFFH
Note
Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction.
Data Sheet U10165EJ2V0DS00
19
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 5-2. Program Memory Map (PD750066)
Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0 0 0 6 H MBE RBE 0 INT1 INT1 0 0 0 8 H MBE RBE 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) BRCB ! caddr instruction branch address CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR ! addr, BRA ! addr1Note or CALLA ! addr1Note instruction CALL ! addr instruction subroutine entry address BR $ addr instruction relative branch address -15 to -1, +2 to +16
0 0 0 0 H MBE RBE
0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H
0FFFH 1000H BRCB ! caddr instruction branch address 17FFH
Note
Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction.
20
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 5-3. Program Memory Map (PD750068)
Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0 0 0 6 H MBE RBE 0 INT1 INT1 0 0 0 8 H MBE RBE 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) BRCB ! caddr instruction branch address CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR ! addr, BRA ! addr1Note or CALLA ! addr1Note instruction CALL ! addr instruction subroutine entry address BR $ addr instruction relative branch address -15 to -1, +2 to +16
0 0 0 0 H MBE RBE
0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H
0FFFH 1000H BRCB ! caddr instruction branch address 1FFFH
Note
Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction.
Data Sheet U10165EJ2V0DS00
21
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 5-4. Data Memory Map
Data memory 000H General-purpose register area 01FH 020H 256 x 4 (224 x 4) Stack area Data area static RAM (512 x 4)
Note
Memory bank
(32 x 4)
0
0FFH 100H
256 x 4
1
1FFH Not incorporated
F80H
Peripheral hardware area
128 x 4
15
FFFH
Note
Memory bank 0 or 1 can be selected as the stack area.
22
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6. PERIPHERAL HARDWARE FUNCTION 6.1 Port
The following three types of I/O ports are available. * CMOS input (PORT0, 1, 11) * CMOS input/output (PORT2, 3, 6) * N-ch open-drain input/output (PORT4, 5) Total : 12 : 12 :8 32 Table 6-1. Types and Features of Digital Ports
Port Name PORT0 Function 4-bit input Operation and Features Remarks
When the serial interface function is used, the alternate-function Also used for the INT4, SCK, pins function as output ports depending on the operation mode. SO/SB0, SI/SB1 pins. 4-bit input only port. Also used for the INT0 to INT2/TI1, TI0 pins. Also used for the PTO0, PTO1, PCL, BUZ pins. -
PORT1
PORT2
4-bit input/output Can be set to input mode or output mode in 4-bit units.
PORT3 PORT4 PORT5 4-bit input/output (N-ch open drain, 13 V withstand voltage)
Can be set to input mode or output mode in 1-bit units. Can be set to input mode or output mode in 4-bit units. On-chip pull-up resistor can be specified in 1-bit units by mask option. Ports 4 and 5 are paired and data can be input/ output in 8-bit units.
PORT6
4-bit input/output Can be set to input mode or output mode in 1-bit units.
Also used for the KR0 to KR3, AN4 to AN7 pins. Also used for the AN0 to AN3 pins.
PORT11
4-bit input
4-bit input only port.
6.2 Clock Generator
The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Figure 6-1 shows the configuration of the clock generator. Operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). Two types of system clocks are available; main system clock and subsystem clock. The instruction execution time can be changed. * 0.95 s, 1.91 s, 3.81 s, 15.3 s (@ 4.19-MHz operation with main system clock) * 0.67 s, 1.33 s, 2.67 s, 10.7 s (@ 6.0-MHz operation with main system clock) * 122 s (@ 32.768-kHz operation with subsystem clock)
Data Sheet U10165EJ2V0DS00
23
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 6-1. Clock Generator Block Diagram
XT1 Subsystem clock oscillator fXT Watch timer * Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * INT0 noise eliminator * Clock output circuit
XT2 X1
X2
Main system clock oscillator
fX
1/1 to 1/4096 Divider 1/2 1/4 1/16
Selector WM.3 SCC SCC3
Internal bus
Oscillation stop Selector
Divider 1/4 * CPU * INT0 noise eliminator * Clock output circuit
SCC0 PCC PCC0 PCC1 4 PCC2 HALTNote PCC3 STOPNote R Q HALT F/F S
PCC2, PCC3 Clear
STOP F/F Q S
Wait release signal from BT RESET signal
R
Standby release signal from interrupt control circuit
Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor Clock Control Register SCC: System Clock Control Register One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
24
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.3 Subsystem Clock Oscillator Control Function
The subsystem clock oscillator of the PD750068 has the following two control functions to decrease the supply current. * Selects by software whether an internal feedback resistor is to be used or notNote. * Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (VDD 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor) by software, connect XT1 to VSS, and open XT2. consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (Refer to Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator This makes it possible to reduce the current
SOS.0
Feedback resistor Inverter SOS.1 XT1 XT2
Data Sheet U10165EJ2V0DS00
25
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.4 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the P22/PCL pin to the remote control wave output applications and peripheral LSIs. * Clock output (PCL) : , 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19-MHz operation) : , 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0-MHz operation) Figure 6-3. Clock Output Circuit Block Diagram
From clock generator fX/22 Selector fX/24 fX/26 PCL/P22 Output buffer
PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch
Bit 2 of PMGB Port 2 I/O mode specification bit
4 Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable.
26
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.5 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (d) Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram
From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear
Basic interval timer (8-bit frequency divider)
Set
BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal
Wait release signal when standby is released
BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 8 Internal bus
WDTM SET1Note 1
Note Instruction execution
Data Sheet U10165EJ2V0DS00
27
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.6 Watch Timer
The PD750068 has one channel of watch timer. The watch timer has the following functions. (a) Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW. (b) 0.5 sec interval can be created by both the main system clock (4.194304 MHz) and subsystem clock (32.768 kHz). (c) Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. (d) Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of system clock frequencies. (e) Clears the frequency divider to make the clock start with zero seconds. (f) Uses the clock of 0.5 sec as the clock source of the timer/event counter to continue the standby mode until the longest time 9 hours (by using timer 0, 1) to be in the lowest consumption mode. Figure 6-5. Watch Timer Block Diagram
fW (256 Hz : 3.91 ms) 27 fX 128 (32.768 kHz) fXT (32.768 kHz)
From clock generator
Selector
fW (32.768 kHz) 4 kHz 2 kHz fW fW 23 24
Divider
fW 214 2 Hz 0.5 sec
Selector INTW IRQW set signal
Clear
Selector
Output buffer P23/BUZ
WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3 P23 output latch
PMGB bit 2 Port 2 input/ output mode
8
Bit test instruction
Internal bus
Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz and fXT = 32.768 kHz.
28
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.7 Timer/Event Counter
The PD750068 has two channels of timer/event counters. Its configuration is shown in Figures 6-6 and 6-7. The timer/event counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to the PTOn pin (n = 0, 1) (c) Event counter operation (d) Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). (e) Supplies the shift clock to the serial interface circuit. (f) Reads the count value.
The timer/event counter operates in the following two modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter
Channel Channel 0 Mode 8-bit timer/event counter mode 16-bit timer/event counter mode Yes Yes Yes Channel 1
Data Sheet U10165EJ2V0DS00
29
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 6-6. Timer/Event Counter Block Diagram (Channel 0)
Internal bus 8
-
TM0
TM06 TM05 TM04 TM03 TM02 TM01 TM00
8 TMOD0 Modulo register (8)
TOE0 TO enable flag
P20 output latch
PORT2.0 PMGB bit 2 Port 2 input/ output mode
Decoder
PORT1. 3
8 Comparator (8) Match TOUT
F/F Output buffer
P20/PTO0
Input buffer
8 T0 Count register (8) Clear
Reset TOUT0 Overflow
TI0/P13
Watch timer (INTW) output
To serial interface Timer/event counter (channel 1) clock input INTT0 (IRQT0 set signal) IRQT0 clear signal RESET
fX/22 4 From clock fX/26 fX/2 generator fX/28 fX/210
MPX
CP
16-bit timer/event counter mode Timer operation start
Timer/event counter (channel 1) TM12 signal (When 16-bit timer/event counter mode)
Timer/event counter (channel 1) match signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) clear signal (When 16-bit timer/event counter mode)
30
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 6-7. Timer/Event Counter Block Diagram (Channel 1)
Internal bus 8 TM1 - TM16 TM15 TM14 TM13 TM12 TM11 TM10 Decoder 8 TMOD1
PORT1.2 TOE1 PORT2.1 PMGB bit 2 Port 2 input/output mode
TO enable flag
P21 output latch
Modulo register (8) 8
Input buffer TI1/P12/INT2
Timer/event counter output (channel 0)
Comparator (8) 8 MPX CP T1
Match
TOUT F/F
P21/PTO1 Output buffer
Reset
fX/22 fX/26 From clock fX/28 generator fX/210 fX/212
Count register (8) Clear
RESET Timer operation start 16 bit timer/event counter mode Selector IRQT1 clear signal
Timer/event counter (channel 0) TM02 signal (When 16-bit timer/event counter mode) Timer/event counter (channel 0) match signal/operation start (When 16-bit timer/event counter mode)
INTT1 IRQT1 set signal
Timer/event counter (channel 0) comparator (When 16-bit timer/event counter mode)
Data Sheet U10165EJ2V0DS00
31
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.8 Serial Interface
The serial interface has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode The 3-wire serial I/O mode enables connections to be made with the 75X Series, 78K Series, and many other types of I/O devices. The 2-wire serial I/O mode enables communication with two or more devices. Figure 6-8. Serial Interface Block Diagram
Internal bus 8/4 CSIM Bit test 8 8 Bit manipulation SBIC
RELT P03/SI/SB1
Selector
CMDT SO latch Q
SET CLR
Shift register (SIO)
(8)
D
P02/SO/SB0
P01/SCK
Selector
Serial clock counter P01 Output latch
INTCSI control circuit
INTCSI IRQCSI set signal Serial clock selector fX/23 fX/24 fX/26 TOUT0 From timer/event counter 0
Serial clock control circuit
External SCK
32
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.9 A/D Converter
The PD750068 incorporates the 8-bit resolution A/D converter which has eight channels analog input pins (AN0 to AN7). This A/D converter is a successive approximation type. Figure 6-9. A/D Converter Block Diagram
Internal bus
8
ADEN ADM6 ADM5 ADM4 SOC
EOC
0
0
8
AN0/P110 AN1/P111 AN2/P112 Sample hold circuit
Controller
+
AN3/P113 AN4/P60/KR0 AN5/P61/KR1 AN6/P62/KR2 AN7/P63/KR3 Multiplexer
SA register (8)
-
Comparator
8
Tap decoder
AVREF R/2 R R R R/2
AVSS ADEN
Data Sheet U10165EJ2V0DS00
33
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.10 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-10. Bit Sequential Buffer Format
Address Bit Symbol 3
FC3H 2 1 0 3
FC2H 2 1 0 3
FC1H 2 1 0 3
FC0H 2 1 0
BSB3
BSB2
BSB1
BSB0
L register
L = FH
L = CH L = BH
L = 8H
L = 7H
L = 4H L = 3H DECS L
L = 0H
INCS L
Remarks 1. 2.
In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.
34
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
7. INTERRUPT FUNCTION AND TEST FUNCTION
The PD750068 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge detection testable inputs. The interrupt control circuit of the PD750068 has the following functions. (1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQxxx). An interrupt generated can be checked by software. * Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQxxx) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag.
Data Sheet U10165EJ2V0DS00
35
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal bus
2
1
4
IME IPS
Interrupt enable flag (IExxx )
IST1 IST0
IM2
IM1
IM0
Decoder
INTBT
IRQBT
VRQn
INT4/P00 INT0/P10 INT1/P11
Note
Selector
Both edge detector Edge detector Edge detector
IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQT1 IRQW IRQ2 Priority control circuit Vector table address generator
INTCSI INTT0 INTT1 INTW INT2/P12
Rising edge detector
Selector
KR0/P60 KR3/P63
Falling edge detector
Standby release signal
IM2
Note
Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.)
36
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
8. STANDBY FUNCTION
In order to save power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD750068. Table 8-1. Operation Status in Standby Mode
Mode Item Set instruction System clock when set STOP Mode STOP instruction Settable only when the main system clock is used. The main system clock stops oscillation. HALT Mode HALT instruction Settable both by the main system clock and subsystem clock. Only the CPU clock halts (oscillation continues). Operable only when the main system clock is oscillated (The IRQBT is set in the reference time interval). Serial interface Operable only when an external SCK input is selected as the serial clock. Operable only when an external SCK input is selected as the serial clock or when the main system clock is oscillated. Operable only when a signal input to the TI0 and TI1 pins or a watch timer which selected fXT is specified as the count clock or when the main system clock is oscillated. Operable.
Operation status
Clock generator
Basic interval timer/ watchdog timer
Operation stops.
Timer/event counter
Operable only when a signal input to the TI0 and TI1 pins or a watch timer which selected fXT is specified as the count clock.
Watch timer
Operable when fXT is selected as the count clock. Operation stops.
A/D converter
Operable only when the main system clock is oscillated.
External interrupt
The INT1, 2, and 4 are operable. Only the INT0 is not operatedNote. Operation stops. * Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag. * Test request signal sent from the test source enabled by the test enable flag * RESET signal generation
CPU Release signal
Note
Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0).
Data Sheet U10165EJ2V0DS00
37
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
9. RESET FUNCTION
There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the configuration of the above two inputs. Figure 9-1. Configuration of Reset Function
RESET
Internal reset signal
Reset signal sent from the basic interval timer/watchdog timer WDTM
Internal bus
When the RESET signal is generated, each hardware is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation
WaitNote
RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode
Note
The following two times can be selected by the mask option. 2 17/fX (21.8 ms: @6.0-MHz operation, 31.3 ms: @4.19-MHz operation) 2 15/fX (5.46 ms: @6.0-MHz operation, 7.81 ms: @4.19-MHz operation)
38
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Table 9-1. Status of Each Hardware After Reset (1/2)
RESET Signal Generation in Standby Mode RESET Signal Generation in Operation Sets the low-order 4 bits of program memory's address 0000H to the PC11 to PC8 and the contents of address 0001H to the PC7 to PC0. Sets the low-order 5 bits of program memory's address 0000H to the PC12 to PC8 and the contents of address 0001H to the PC7 to PC0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0
Hardware Program counter (PC)
PD750064
Sets the low-order 4 bits of program memory's address 0000H to the PC11 to PC8 and the contents of address 0001H to the PC7 to PC0.
PD750066, Sets the low-order 5 bits of 750068 program memory's address 0000H to the PC12 to PC8 and the contents of address 0001H to the PC7 to PC0.
PSW Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0
Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/event counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Watch timer Mode register (WM)
Data Sheet U10165EJ2V0DS00
39
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Table 9-1. Status of Each Hardware After Reset (2/2)
RESET Signal Generation in Standby Mode Held 0 0 0 0 0 0 04H 7FH Reset (0) 0 0 0, 0, 0 Off Cleared (0) 0 0 Held RESET Signal Generation in Operation Undefined 0 0 0 0 0 0 04H 7FH Reset (0) 0 0 0, 0, 0 Off Cleared (0) 0 0 Undefined
Hardware Serial interface Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Clock generator, clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM)
Sub-oscillator control register (SOS) A/D converter Mode register (ADM) SA register (SA) Interrupt function Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt priority selection register (IPS) INT0, 1, 2 mode registers (IM0, IM1, IM2) Digital port Output buffer Output latch I/O mode registers (PMGA, PMGB) Pull-up resistor setting register (POGA) Bit sequential buffer (BSB0 to BSB3)
40
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
10. MASK OPTION
The PD750068 has the following mask options. * Mask option of P40 to P43 and P50 to P53 Can select whether to incorporate the pull-up resistor. (1) The pull-up resistor is incorporated in 1-bit units. (2) The pull-up resistor is not incorporated. * Mask option of standby function Can select the wait time with the RESET signal. (1) 2 17/fX (21.8 ms at fX = 6.0 MHz, 31.3 ms at fX = 4.19 MHz) (2) 2 15/fX (5.46 ms at fX = 6.0 MHz, 7.81 ms at fX = 4.19 MHz) * Mask option of subsystem clock Can select whether to enable the internal feedback resistor. (1) The internal feedback resistor is enabled (switch internal feedback resistor ON/OFF by software). (2) The internal feedback resistor is disabled (disconnect internal feedback resistor by hardware).
Data Sheet U10165EJ2V0DS00
41
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
11. INSTRUCTION SET
(1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to "RA75X Assembler Package User's Manual----Language (U12385E)". If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers or labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see
PD750068 User's Manual (U10670E).
Expression Format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr, addr1 (Mk II mode only) caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, BC, XA, BC, DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL'
Description Method
HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label 0000H to 0FFFH 0000H to 17FFH 0000H to 1FFFH 12-bit immediate 11-bit immediate immediate data or label (PD750064) immediate data or label (PD750066) immediate data or label (PD750068) data or label data or label
20H to 7FH immediate data (where bit0 = 0) or label PORT0 to PORT6, PORT11 IEBT, IET0, IET1, IE0 to IE2, IE4, IECSI, IEW RB0 to RB3 MB0, MB1, MB15
Note
mem can be only used for even address in 8-bit data processing.
42
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
(2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' expanded register pair : BC' expanded register pair : DE' expanded register pair : HL' expanded register pair : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 0 to 6, 11) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by xx : Hexadecimal data
Data Sheet U10165EJ2V0DS00
43
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
(3) Explanation of symbols under addressing area column
*1 *2 *3 MB = MBE*MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 0FFFH (PD750064) 0000H to 17FFH (PD750066) 0000H to 1FFFH (PD750068) addr, addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 caddr = 0000H 0000H 1000H 1000H to to to to 0FFFH 0FFFH 17FFH 1FFFH (PD750064) (PC12 = 0: PD750066, 750068) (PC12 = 1: PD750066) (PC12 = 1: PD750068)
Data memory addressing
*4 *5 *6
*7
*8
Program memory addressing
*9 *10 *11
faddr = 0000H to 07FFH taddr = 0020H to 007FH Mk II mode only addr1 = 0000H to 0FFFH (PD750064) 0000H to 17FFH (PD750066) 0000H to 1FFFH (PD750068)
Remarks 1. 2. 3. 4.
MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed.
(4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * * * When no skip is made: S = 0 When the skipped instruction is a 1- or 2-byte instruction: S = 1 When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle (= tCY) of CPU clock ; time can be selected from among four types by setting PCC.
44
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B
Instruction Group Transfer
Mnemonic
Operand
Number of Bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2
Operation
Addressing Area
Skip Condition
MOV
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA
String effect A
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
Data Sheet U10165EJ2V0DS00
45
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 3
Instruction Group Table reference
Mnemonic
Operand
Number of Bytes 1
Operation
Addressing Area
Skip Condition
MOVT
XA, @PCDE
PD750064 XA (PC11-8+DE)ROM PD750066, 750068 XA (PC12-8+DE)ROM
XA, @PCXA
1
3
PD750064 XA (PC11-8+XA)ROM PD750066, 750068 XA (PC12-8+XA)ROM
XA, @BCDE XA, @BCXA Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA
1 1 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2
3 3 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2
XA (BCDE)ROMNote XA (BCXA)ROMNote CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY
*6 *6 *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
*1
borrow borrow borrow
*1
Note
Set "0" to register B if the PD750064 is used. Only low-order one bit of register B will be valid if the
PD750066, 750068 is used.
46
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY CY = 1 *1 *1 *1 *1 *3 reg = 0 rp1 = 00H (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' *1 *1 *1
Instruction Group Operation
Mnemonic
Operand
Number of Bytes 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
Operation
Addressing Area
Skip Condition
AND
A, #n4 A, @HL XA, rp' rp'1, XA
OR
A, #n4 A, @HL XA, rp' rp'1, XA
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
Accumulator manipulation
RORC NOT
A A reg rp1 @HL mem
Increment and Decrement
INCS
DECS
reg rp'
Comparison
SKE
reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY
Data Sheet U10165EJ2V0DS00
47
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2+L3-2.bit(L1-0)) CY CY v (H+mem3-0.bit)
Instruction Group Memory bit manipulation
Mnemonic
Operand
Number of Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Operation
Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip Condition
SET1
mem.bit fmem.bit pmem.@L @H+mem.bit
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
(mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR
fmem.bit pmem.@L @H+mem.bit
AND1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
OR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
XOR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
48
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles -
Instruction Group Branch
Mnemonic
Operand
Number of Bytes -
Operation
Addressing Area *6
Skip Condition
BRNote
addr
PD750064 PC11-0 addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. PD750066, 750068 PC12-0 addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used.
addr1
-
-
PD750064 PC11-0 addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. PD750066, 750068 PC12-0 addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used.
*11
! addr
3
3
PD750064 PC11-0 addr PD750066, 750068 PC12-0 addr
*6
$addr
1
2
PD750064 PC11-0 addr PD750066, 750068 PC12-0 addr
*7
$addr1
1
2
PD750064 PC11-0 addr1 PD750066, 750068 PC12-0 addr1
Note
The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
Data Sheet U10165EJ2V0DS00
49
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 3
Instruction Group Branch
Mnemonic
Operand
Number of Bytes 2
Operation
Addressing Area
Skip Condition
BR
PCDE
PD750064 PC11-0 PC11-8+DE PD750066, 750068 PC12-0 PC12-8+DE
PCXA
2
3
PD750064 PC11-0 PC11-8+XA PD750066, 750068 PC12-0 PC12-8+XA
BCDE
2
3
PD750064 PC11-0 BCDENote 1 PD750066, 750068 PC12-0 BCDENote 2
*6
BCXA
2
3
PD750064 PC11-0 BCXANote 1 PD750066, 750068 PC12-0 BCXANote 2
*6
BRANote 3
3
3
PD750064 PC11-0 addr1 PD750066, 750068 PC12-0 addr1
*11
BRCB
!caddr
2
2
PD750064 PC11-0 caddr11-0 PD750066, 750068 PC12-0 PC12+caddr11-0
*8
Subroutine stack control
CALLANote 3
!addr1
3
3
PD750064 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr1, SP SP-6 PD750066, 750068 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 PC12-0 addr1, SP SP-6
*11
Notes 1. 2. 3.
"0" must be set to B register. Only low-order one bit is valid in B register. The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
50
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 3
Instruction Group Subroutine stack control
Mnemonic CALLNote
Operand
Number of Bytes 3
Operation
Addressing Area *6
Skip Condition
!addr
PD750064 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 addr, SP SP-4 PD750066, 750068 (SP-3) MBE, RBE, 0, PC12 (SP-4) (SP-1) (SP-2) PC11-0 PC12-0 addr, SP SP-4
4
PD750064 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr, SP SP-6 PD750066, 750068 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 PC12-0 addr, SP SP-6
CALLFNote
!faddr
2
2
PD750064 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 0+faddr, SP SP-4 PD750066, 750068 (SP-3) MBE, RBE, 0, PC12 (SP-4) (SP-1) (SP-2) PC11-0 PC12-0 00+faddr, SP SP-4
*9
3
PD750064 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 0+faddr, SP SP-6 PD750066, 750068 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 PC12-0 00+faddr, SP SP-6
Note
The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
Data Sheet U10165EJ2V0DS00
51
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 3
Instruction Group Subroutine stack control
Mnemonic
Operand
Number of Bytes 1
Operation
Addressing Area
Skip Condition
RETNote
PD750064 PC11-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 PD750066, 750068 PC11-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, PC12 (SP+1), SP SP+4 PD750064 x, x, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC11-0 (SP) (SP+3) (SP+2), SP SP+6 PD750066, 750068 x, x, MBE, RBE (SP+4) MBE, 0, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2), SP SP+6
RETSNote
1
3+S
PD750064 MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally PD750066, 750068 MBE, RBE, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally PD750064 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+6 then skip unconditionally PD750066, 750068 0, 0, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+4 then skip unconditionally
Unconditional
Note
The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
52
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 3
Instruction Group Subroutine stack control
Mnemonic RETINote 1
Operand
Number of Bytes 1
Operation
Addressing Area
Skip Condition
PD750064 MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PD750066, 750068 MBE, RBE, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PD750064 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PD750066, 750068 0, 0, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6
PUSH
rp BS
1 2 1 2 2
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2
(SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1) (SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n MBS n (n = 0-3) (n = 0, 1, 15) (n = 0-6, 11) (n = 4) (n = 2-6) (n = 4)
POP
rp BS
Interrupt control
EI IExxx DI IExxx
2 2 2 2 2 2 2 2 2 1
Input/output
IN
Note 2
A, PORTn XA, PORTn
OUTNote 2
PORTn, A PORTn, XA
CPU control
HALT STOP NOP
Special
SEL
RBn MBn
2 2
Notes 1. 2.
The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and MBS must be set to 15.
Data Sheet U10165EJ2V0DS00
53
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Number of Machine Cycles 3
Instruction Group Special
Mnemonic GETINotes 1, 2
Operand
Number of Bytes 1
Operation
Addressing Area *10
Skip Condition
taddr
PD750064 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1)
----------------------------------
-------------
* When TCALL instruction (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 (taddr) 3-0 + (taddr+1) SP SP-4
---------------------------------- -------------
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed.
Depending on the reference instruction
PD750066, 750068 * When TBR instruction PC12-0 (taddr) 4-0 + (taddr+1)
---------------------------------- -------------
* When TCALL instruction (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 (taddr) 4-0 + (taddr+1) SP SP-4
---------------------------------- -------------
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3
Depending on the reference instruction *10
PD750064 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1)
* When TCALL instruction (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 (SP-2) x, x, MBE, RBE PC11-0 (taddr) 3-0 + (taddr+1) SP SP-6
-----------------------------------------
-------------
4
-----------------------------------------
-------------
3
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed.
Depending on the reference instruction
3
PD750066, 750068 * When TBR instruction PC12-0 (taddr) 4-0 + (taddr+1)
-------------
-----------------------------------------
4
* When TCALL instruction (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 (SP-2) x, x, MBE, RBE PC12-0 (taddr) 4-0 + (taddr+1) SP SP-6
-------------
-----------------------------------------
3
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed.
Depending on the reference instruction
Notes 1. 2.
The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
54
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Other than ports 4, 5 Ports 4, 5 Pull-up resistor provided N-ch open drain Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 Per pin Total of all pins Output current, low IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg -10 -30 30 220 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA C C
Output voltage Output current, high
VO IOH
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Data Sheet U10165EJ2V0DS00
55
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Recommended Constants
Resonator Ceramic resonator
Parameter Oscillation frequency (fX)Note 1
Conditions
MIN. 1.0
TYP.
MAX.
Unit
6.0Note 2 MHz
X1
X2
C1
C2
Oscillation stabilization timeNote 3 Oscillation frequency (fX)Note 1
After VDD reaches oscillation voltage range MIN. value 1.0
4
ms
Crystal resonator
X1 X2
6.0Note 2 MHz
C1
C2
Oscillation stabilization timeNote 3
VDD = 4.5 to 5.5 V
10 30
ms
External clock
X1 input frequency (fX)Note 1
1.0
6.0Note 2 MHz
X1
X2
X1 input high-/ low-level width (tXH, tXL) 83.3 500 ns
Notes 1. 2.
The oscillation frequency and X1 input frequency shown above indicate only oscillator characteristics. Refer to AC Characteristics for instruction execution time. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, do not select the processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle time is less than 0.95 s, falling short of the rated value of 0.95 s.
3.
The oscillation stabilization time is the time required to stabilize oscillation after VDD has been applied or STOP mode has been released.
Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
56
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Recommended Constants
Resonator Crystal resonator
Parameter Oscillation frequency (fXT)Note 1
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
XT1
XT2 R
C3
C4
Oscillation stabilization timeNote 2
VDD = 4.5 to 5.5 V
1.0
2 10
s
External clock
XT1 XT2
XT1 input frequency (fXT)Note 1
32
100
kHz
XT1 input high-/ low-level width (tXTH, tXTL)
5
15
s
Notes 1. 2.
The oscillation frequency and XT1 input frequency shown above indicate only oscillator characteristics. Refer to AC Characteristics for instruction execution time. The oscillation stabilization time is the time required to stabilize oscillation after VDD has been applied.
Caution When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used.
Data Sheet U10165EJ2V0DS00
57
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C)
Oscillator Constant (pF) C1 Murata Mfg. Co., Ltd. CSB1000JNote CSA2.00MG040 CST2.00MG040 CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU Kyocera Corp. KBR-1000F/Y KBR-2.0MS KBR-4.19MSA KBR-6.0MSA TDK CCR1000K2 CCR2.0MC33 CCR4.19MC3 FCR4.19MC5 CCR6.0MC3 FCR6.0MC5 6.0 1.0 2.0 4.19 6.0 1.0 2.0 4.19 2.2 2.0 2.2 6.0 4.19 1.0 2.0 100 100 - 30 - 30 - 30 - 30 - 100 68 33 33 100 - C2 100 100 - 30 - 30 - 30 - 30 - 100 68 33 33 100 - 1.8 2.0 5.5 - Capacitor-contained model 1.8 1.95 1.8 5.5 2.4 3.0 1.8 1.9 Oscillation Voltage Range (VDD) MIN. 2.0 2.3 MAX. 5.5 Rd = 1 k - Capacitor-contained model - Capacitor-contained model - Capacitor-contained model - Capacitor-contained model - Capacitor-contained model -
Manufacturer
Part Number
Frequency (MHz)
Remarks
Note
When using the CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 1 k) is necessary (refer to the figure below). The limiting resistor is not necessary when using the other recommended resonators.
X1 CSB1000J C1 X2 Rd C2
Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee precision of the oscillation frequency. If the application circuit requires precision of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used.
58
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, low Symbol IOL Per pin Total of all pins Input voltage, high VIH1 Ports 2, 3, 11 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIH2 Ports 0, 1, 6, RESET 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIH3 Ports 4, 5 Pull-up resistor provided N-ch open drain 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIH4 Input voltage, low VIL1 X1, XT1 Ports 2, 3, 4, 5, 11 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIL2 Ports 0, 1, 6, RESET 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIL3 Output voltage, high VOH Output voltage, low VOL1 X1, XT1 SCK, SO, ports 2, 3, 6 IOH = -1.0 mA IOL = 15 mA VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 N-ch open drain Pull-up resistor 1 k Input leakage current, high ILIH1 ILIH2 ILIH3 Input leakage current, low ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1, XT1 X1, XT1 Ports 4, 5 (N-ch open drain) Pins other than ports 4, 5, X1, XT1 X1, XT1 Ports 4, 5 (N-ch open drain) When input instruction is not executed Ports 4, 5 (N-ch open drain) When input instruction is executed Output leakage current, high ILOH2 Output leakage current, low Internal pull-up resistor RL1 RL2 VIN = 0 V Ports 0, 1, 2, 3, 6 (except pin P00) Ports 4, 5 (Mask option) 50 15 100 30 200 60 k k ILOL ILOH1 VOUT = VDD -30 VDD = 5.0 V VDD = 3.0 V -10 -3 -27 -8 3 3 20 20 -3 -20 -3 0.4 0.2VDD V V 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0.7VDD 0.9VDD 0.7VDD 0.9VDD VDD-0.1 0 0 0 0 0 VDD-0.5 0.2 2.0 Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V
SCK, SO, ports 2, 3, 4, 5, 6
A A A A A A A A A A A A
SCK, SO/SB0, SB1, ports 2, 3, 6, ports 4, 5 (Pull-up resistor provided)
VOUT = 13 V Ports 4, 5 (N-ch open drain) VOUT = 0 V
20 -3
Data Sheet U10165EJ2V0DS00
59
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Supply currentNote 1 Symbol IDD1
6.0-MHz Note 2 crystal oscillation C1 = C2 = 22 pF 4.19-MHz crystal oscillation C1 = C2 = 22 pF
Note 2
Conditions VDD = 5.0 V 10%Note 3 VDD = 3.0 V 10%Note 4 HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% 10%Note 3
MIN.
TYP. 2.2 0.48 0.86 0.43 1.7 0.4 0.7 0.39 11 5.5 11 9.2 9.2 6.4 2.5 6.4 4.6 4.6 0.05 0.02
MAX. 6.6 1.5 2.6 1.3 4.5 1.2 2 1.2 33 17 22 27 18 20 8 12.8 13.8 9.2 10 5 3
Unit mA mA mA mA mA mA mA mA
IDD2
IDD1
VDD = 5.0 V
VDD = 3.0 V 10%Note 4 HALT mode Lowvoltage modeNote 6
Low current dissipation mode Note 7
IDD2
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25C VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C Lowvoltage
Low current dissipation mode Note 7
IDD3
32.768kHzNote 5 crystal oscillation
A A A A A A A A A A A A A
IDD4
HALT mode
VDD = 3.0 V 10% VDD = 2.0 V 10%
modeNote 6 VDD = 3.0 V, TA = 25C
VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C
IDD5
XT1 = 0 VNote 8 STOP mode
VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25C
0.02
Notes 1. 2. 3. 4. 5. 6. 7. 8.
The current flowing to the internal pull-up resistor is not included. Including the case when the subsystem clock oscillates. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. When the device operates in low-speed mode with PCC set to 0000. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. When the sub-oscillation circuit control register (SOS) is set to 0000. When SOS is set to 0010. When SOS is set to 00x1, and the sub-oscillation circuit feedback resistor is not used (x: don't care).
60
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter CPU clock cycle timeNote 1 tCY Symbol
Operates with main system clock Operates with subsystem clock
Conditions VDD = 2.7 to 5.5 V
MIN. 0.67 0.95 114
TYP.
MAX. 64 64
Unit
s s s
MHz kHz
(minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency fTI
122
125
VDD = 2.7 to 5.5 V
0 0
1.0 275
TI0, TI1 input high-/low-level width Interrupt input high-/ low-level width
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.48 1.8
s s s s s s s
tINTH, tINTL
INT0
IM02 = 0 IM02 = 1
Note 2 10 10 10 10
INT1, 2, 4 KR0 to 3 RESET low-level width tRSL
Notes 1.
The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock.
Cycle time tCY [ s] 4 3 64 60 6 5
tCY vs VDD (with main system clock)
Guaranteed operation range
2.
2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
2
1
0.5
0
1
2
3
4
5
6
Supply voltage VDD [V]
Data Sheet U10165EJ2V0DS00
61
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK *** internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-/low-level width SI Note 1 SI Note 1 setup time (to SCK ) hold time SONote 1 tKL1, tKH1 tSIK1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 150 500 tKSI1 VDD = 2.7 to 5.5 V
Note 2
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
400 600
(from SCK ) SCK output tKSO1 RL = 1 k, VDD = 2.7 to 5.5 V delay time CL = 100 pF
0 0
250 1000
ns ns
Notes 1. 2.
Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL are the load resistance and load capacitance of the SO output line.
2-wire and 3-wire serial I/O modes (SCK *** external clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-/low-level width SI Note 1 setup time (to SCK ) tKL2, tKH2 tSIK2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 400 1600 100 150 SI Note 1 hold time (from SCK ) SCK SONote 1 output delay time tKSO2 RL = 1 k,
Note 2
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKSI2
VDD = 2.7 to 5.5 V
400 600 VDD = 2.7 to 5.5 V 0 0 300 1000
ns ns
CL = 100 pF
Notes 1. 2.
Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL are the load resistance and load capacitance of the SO output line.
62
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
A/D Converter Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V, 1.8 V AVREF VDD)
Parameter Resolution Absolute accuracyNote 1 VDD = AVREF VDD AVREF Conversion time Sampling time Analog input voltage Analog input impedance AVREF current tCONV tSAMP VIAN RAN IREF Note 2 Note 3 AVSS 1000 0.25 2.0 2.7 V VDD 1.8 V VDD < 2.7 V Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.5 3 3 168/fX 44/fX AVREF Unit bit LSB LSB LSB
s s
V M mA
Notes 1. 2. 3.
Absolute accuracy excluding quantization error (1/2LSB) Time until end of conversion (EOC = 1) after execution of conversion start instruction (40.1 s: fX = 4.19 MHz). Time until end of sampling after execution of conversion start instruction (10.5 s: fX = 4.19 MHz).
Data Sheet U10165EJ2V0DS00
63
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
AC timing test points (excluding X1 and XT1 inputs)
VIH (MIN.) VIL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VOH (MIN.) VOL (MAX.)
Clock timing
1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V
1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V
TI0, TI1 timing
1/fTI tTIL tTIH
TI0, TI1
64
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Serial transfer timing 3-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SI
Input data
tKSO1, 2
SO
Output data
2-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0, 1
tKSO1, 2
Data Sheet U10165EJ2V0DS00
65
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Interrupt input timing
tINTL tINTH
INT0, 1, 2, 4 KR0 to 3
RESET input timing
tRSL
RESET
66
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Release signal set time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 0 Note 2 Note 3 TYP. MAX. Unit
s
ms ms
Notes 1. 2. 3.
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. Either 2 17/fX or 215/fX can be selected by mask option. Set by the basic interval timer mode register (BTM). (Refer to the table below.)
Wait Time fX = 4.19 MHz - - - - 0 0 1 1 0 1 0 1 0 1 1 1 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.81 ms) 213/fX (approx. 1.95 ms) fX = 6.0 MHz 220/fX (approx. 175 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.37 ms)
BTM3
BTM2
BTM1
BTM0
Data retention timing (STOP mode release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD STOP instruction execution
VDDDR
tSREL
RESET tWAIT
Data retention timing (standby release signal: STOP mode release by interrupt signal)
HALT mode STOP mode Data retention mode Operation mode
VDD STOP instruction execution Standby release signal (interrupt request)
VDDDR
tSREL
tWAIT
Data Sheet U10165EJ2V0DS00
67
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
13. CHARACTERISTICS CURVES (REFERENCE VALUES)
IDD vs VDD (main system clock: 6.0-MHz crystal resonator)
(TA = 25C) 10
5.0
PCC = 0011 PCC = 0010 PCC = 0001 1.0 PCC = 0000 Main system clock HALT mode + 32-kHz oscillation
0.5
Supply Current IDD (mA)
0.1
0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1)
0.01
0.005
X1
Crystal resonator
X2 XT1
6.0 MHz
XT2 330 k 33 pF
32.768 kHz
Crystal resonator
22 pF
22 pF
33 pF
0.001
0
1
2
3
4 Supply Voltage VDD (V)
5
6
7
8
68
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
IDD vs VDD (main system clock: 4.19-MHz crystal resonator)
(TA = 25C) 10
5.0
PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32-kHz oscillation
0.5
Supply Current IDD (mA)
0.1
0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1)
0.01
0.005
X1
Crystal resonator
X2 XT1
4.19 MHz
XT2 330 k 33 pF
32.768 kHz
Crystal resonator
22 pF
22 pF
33 pF
0.001
0
1
2
3
4 Supply Voltage VDD (V)
5
6
7
8
Data Sheet U10165EJ2V0DS00
69
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
14. PACKAGE DRAWINGS 42 PIN PLASTIC SHRINK DIP (600 mil)
42
22
1 A
21
K L I G J H
F C D N
M
B M
R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15
INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15 P42C-70-600A-1
70
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
42 PIN PLASTIC SHRINK SOP (375 mil)
42
22 detail of lead end
1
A
21 H I
G
3 +7 -3
J
F
E
C D M
M
N
B
K
L S42GT-80-375B-1
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N
MILLIMETERS 18.16 MAX. 1.13 MAX. 0.8 (T.P.) 0.35 +0.10 -0.05 0.125 0.075 2.9 MAX. 2.5 0.2 10.3 0.3 7.15 0.2 1.6 0.2 0.15 +0.10 -0.05 0.8 0.2 0.10 0.10
INCHES 0.715 MAX. 0.044 MAX. 0.031 (T.P.) 0.014 +0.004 -0.003 0.005 0.003 0.115 MAX. 0.098+0.009 -0.008 0.406+0.012 -0.013 0.281+0.009 -0.008 0.063 0.008 0.006 +0.004 -0.002 0.031 +0.009 -0.008 0.004 0.004
Data Sheet U10165EJ2V0DS00
71
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
15. RECOMMENDED SOLDERING CONDITIONS
The PD750068 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions
PD750064GT-xxx PD750066GT-xxx PD750068GT-xxx
: 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
PD750064GT(A)-xxx : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) PD750066GT(A)-xxx : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) PD750068GT(A)-xxx : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Recommended Condition Symbol
Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), IR35-00-2 Count: two times or less Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher), VP15-00-2 Count: two times or less Solder bath temperature: 260C Max., Time: 10 sec. Max., Count: once Preheating temperature: 120C Max. (package surface temperature) Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) WS60-00-1
Partial heating
--
Caution Do not use different soldering methods together (except for partial heating). Table 15-2. Through Hole Type Soldering Conditions
PD750064CU-xxx PD750066CU-xxx PD750068CU-xxx
: 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
PD750064CU(A)-xxx : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) PD750066CU(A)-xxx : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) PD750068CU(A)-xxx : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
Soldering Method Wave soldering (pin only) Partial heating Soldering Conditions Solder bath temperature: 260C Max., Time: 10 sec. Max. Pin temperature: 300C Max., Time: 3 sec. Max. (per pin)
Caution In wave soldering, apply solder only to the pins. Care must be taken that jet solder does not come in contact with the main body of the package.
72
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
APPENDIX A. PD75068, 750068 AND 75P0076 FUNCTIONAL LIST
Item Program memory
PD75068
Mask ROM 0000H to 1F7FH (8064 x 8 bits) 000H to 1FFH (512 x 4 bits) 75X Standard CPU 4 bits x 8 or 8 bits x 4 0.95, 1.91, 15.3 s (@4.19-MHz operation) 122 s (@32.768-kHz operation)
PD750068
Mask ROM 0000H to 1FFFH (8192 x 8 bits)
PD75P0076
One-time PROM 0000H to 3FFFH (16384 x 8 bits)
Data memory
CPU General-purpose register Instruction execution time When main system clock is selected When subsystem clock is selected I/O port CMOS input CMOS input/output N-ch open-drain input/output
75XL CPU (4 bits x 8 or 8 bits x 4) x 4 banks * 0.67, 1.33, 2.67, 10.7 s (@6.0-MHz operation) * 0.95, 1.91, 3.81, 15.3 s (@4.19-MHz operation)
12 (on-chip pull-up resistor specified by software: 7) 12 (on-chip pull-up resistor specified by software) 8 (on-chip pull-up resistor specified by mask option) Withstand voltage is 10 V 32 3 * * * channels 8-bit timer/event counter 8-bit basic interval timer Watch timer 4 channels * 8-bit timer/event counter 0 (watch timer output added) * 8-bit timer/event counter 1 (can be used as a 16-bit timer/ event counter) * 8-bit basic interval timer/watchdog timer * Watch timer * 8-bit resolution x 8 channels (successive approximation) * Can operate at the voltage from VDD = 1.8 V 8 (on-chip pull-up resistor specified by mask option) Withstand voltage is 13 V 8 (no mask option) Withstand voltage is 13 V
Total Timer
A/D converter
* 8-bit resolution x 8 channels (successive approximation) * Can operate at the voltage from VDD = 2.7 V
Data Sheet U10165EJ2V0DS00
73
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Item Clock output (PCL)
PD75068
, 524, 262, 65.5 kHz (@4.19-MHz operation with main system clock)
PD750068
PD75P0076
* , 1.05 MHz, 262 kHz, 65.5 kHz (@4.19-MHz operation with main system clock) * , 1.5 MHz, 375 kHz, 93.8 kHz (@6.0-MHz operation with main system clock) * 2, 4, 32 kHz (@4.19-MHz operation with main system clock or @32.768-kHz operation with subsystem clock) * 2.93, 5.86, 46.9 kHz (@6.0-MHz operation with main system clock) 2 modes are available * 3-wire serial I/O mode *** MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode
Buzzer output (BUZ)
2, 4, 32 kHz (@4.19-MHz operation with main system clock or @32.768-kHz operation with subsystem clock) 3 modes are available * 3-wire serial I/O mode *** MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode * SBI mode External: 3, internal: 3 External: 1, internal: 1 VDD = 2.7 to 6.0 V TA = -40 to +85C * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP (10 x 10 mm)
Serial interface
Vectored interrupt Test input Supply voltage Operating ambient temperature Package
External: 3, internal: 4
VDD = 1.8 to 5.5 V
* 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) * 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
74
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD750068. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor
RA75X relocatable assembler Part Number (Product Name)
Host Machine OS PC-9800 Series MS-DOSTM Ver. 3.30 to Ver. 6.2Note IBM PC/ATTM compatible machines Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Supply Media 3.5-inch 2HD 5-inch 2HD
S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X
Device file
Host Machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver.6.2 IBM PC/AT compatible machines
Note
Supply Media 3.5-inch 2HD 5-inch 2HD
Part Number (Product Name)
S5A13DF750068 S5A10DF750068 S7B13DF750068 S7B10DF750068
Refer to "OS for IBM PC"
3.5-inch 2HC 5-inch 2HC
Note
Ver. 5.00 or later has the task swap function, but it cannot be used for this software.
Remark Operation of the assembler and device file is guaranteed only on the above host machines and OSs.
Data Sheet U10165EJ2V0DS00
75
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
PROM write tools
Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single-chip microcontrollers including PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. PROM programmer adapter for the PD75P0076CU and 75P0076GT. programmer adapter to PG-1500 for use. Connect the
PA-75P0076CU
Software
PG-1500 controller
PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host Machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver. 6.2Note IBM PC/AT compatible machines Refer to "OS for IBM PC" 3.5-inch 2HD 5-inch 2HC Supply Media 3.5-inch 2HD 5-inch 2HD Part Number (Product Name)
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
Note
Ver. 5.00 or later has the task swap function, but it cannot be used for this software.
Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.
76
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
PD750068.
The system configurations are described as follows.
Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a PD750068 Subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a PD750068 Subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use a PD750068 Subseries. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD750068CU. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. Emulation probe for the PD750068GT. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the flexible board EV-9500GT-42 which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the IE-75000-R or IE-75001-R on a host machine. Host Machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver. 6.2Note 2 IBM PC/AT compatible machines Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Supply Media 3.5-inch 2HD 5-inch 2HD Part Number (Product Name)
IE-75001-R
EP-750068CU-R
EP-750068GT-R
EV-9500GT-42 Software IE control program
S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X
Notes 1. 2.
Maintenance product Ver. 5.00 or later has the task swap function, but it cannot be used for this software. Operation of the IE control program is guaranteed only on the above host machines and OSs. The PD750064, 750066, 750068, and 75P0076 are commonly referred to as the PD750068 Subseries.
Remarks 1. 2.
Data Sheet U10165EJ2V0DS00
77
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
OS for IBM PC The following IBM PC OS's are supported.
OS PC DOSTM Version Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote J5.02/V Note
MS-DOS
IBM DOS TM
Note Only English version is supported. Caution Ver. 5.0 or later has the task swap function, but it cannot be used for this software.
78
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents related to device
Document No. Document Name Japanese English U10165E (this document) U10232E U10670E - U10453E
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet
U10165J U10232J U10670J IEM-5606 U10453J
PD75P0076 Data Sheet PD750068 User's Manual PD750068 Instruction Table
75XL Series Selection Guide
Documents related to development tool
Document No. Document Name Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-750068CU/GT-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language EEU-846 U11354J U10950J U11940J U12622J U12385J English EEU-1416 U11354E U10950E U11940E U12622E U12385E U12598E
Structured Assembler U12598J Preprocessor PG-1500 Controller User's Manual PC-9800 Series EEU-704 (MS-DOS) Based IBM PC Series EEU-5008 (PC DOS) Based
EEU-1291
U10540E
Other related documents
Document No. Document Name Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System X13769X C10535J C11531J C10983J C10535E C11531E C10983E C11892E - English
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J Guide to Microcomputer-Related Products by Third Party U11416J
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U10165EJ2V0DS00
79
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
80
Data Sheet U10165EJ2V0DS00
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U10165EJ2V0DS00
81
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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